In the semiconductor device disclosed in Japanese unexamined patent publication No. 2002-117699 (Patent Document 1), an initial setting data area for storing initial settings is provided for a memory cell array 110 composed of electrically rewritable non-volatile memory cells, as shown in FIG. 7. A bad column address register 190 is provided for storing bad column addresses corresponding to bad columns which occurred in the memory cell array 110. In addition, trimming data registers 210, 230 are provided for storing adjustment data used for generating various voltages in an internal voltage generator circuit 200 and adjustment data used for generating various timing pulses in a timer circuit 220, respectively.
As a result of wafer test, adjustment data for various voltages generated in the internal voltage generator circuit 200 and adjustment data for various timing pulses generated in the timer circuit 220 are set in the trimming data registers 210, 230, and bad column addresses are set in the bad column address register 190.
The data in the trimming data registers 210, 230 and in the bad column address register 190 are stored as initial settings in the initial setting data area of the memory cell array 110 composed of non-volatile memory cells.
In the image input device disclosed in Japanese unexamined patent publication No. H08(1996)-125914 (Patent Document 2), when the power switch is turned ON to supply system power, a check is made to determine whether a request for updating control information has been input from a remote control unit or externally connected computer, as shown in FIG. 8 (S100 and S200). If an update request has been made, control information stored in RAM is updated or new control information is stored in the RAM, and data on execution of the updating is stored in a specified location of the RAM (S300).
When the power source is turned OFF, the RAM is examined to determine the presence or absence of updated control information (S500). If updating has been done, the control information stored in the RAM is then written into an EEPROM (S600). A voltage retaining circuit is designed to maintain a system power source voltage for a certain period of time until at least the process S600 is completed after turning-OFF of the power switch.